ECE Seminar: Constructing a Processor for Exascale Computing
Friday, March 24, 2017
12:00 pm - 1:00 pm
Hudson Hall 208
Gabriel H. Loh, Fellow Design Engineer, AMD Research
The need for ever more powerful supercomputers does not appear to be slowing down, but the challenges to push computing to exaFLOP levels and beyond are becoming increasingly difficult. Given government targets for computing throughput, memory capacity, memory bandwidth, power efficiency, reliability, and cost, in this talk I will present one possible vision for a processor architecture that can be used to construct exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is a computational building block for an exascale supercomputer. The ENA consists of an Exascale Heterogeneous Processor (EHP) coupled with an advanced memory system. The EHP provides a high-performance accelerated processing unit (CPU+GPU), in-package high-bandwidth 3D memory, and aggressive use of die-stacking and chiplet technologies to meet the requirements for exascale computing in a balanced manner. In addition to detailing our approach, I will also discuss some of the remaining open research challenges for the community.