Daniel J. Sorin

Image of Daniel J. Sorin

W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering

Dr. Daniel Sorin is the W.H. Gardner Jr. professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.

Appointments and Affiliations
  • W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
  • Professor of Electrical and Computer Engineering
  • Associate Professor in the Department of Computer Science
Contact Information:
Education:

  • Ph.D. University of Wisconsin at Madison, 2002
  • M.S. University of Wisconsin at Madison, 1998
  • B.S. Duke University, 1996

Research Interests:

The primary focus of my research is computer architecture. This research includes work to: improve the dependability of computer architectures, design microarchitectures such that their designs are easier to validate, and develop memory system designs for multicore processors.

Specialties:

Computer Engineering
Computer Architecture
Fault Tolerance
Reliability

Courses Taught:
  • ECE 250L: Computer Architecture
  • ECE 552: Advanced Computer Architecture I
  • ECE 554: Fault-Tolerant and Testable Computer Systems
  • ECE 652: Advanced Computer Architecture II

Representative Publications: (More Publications)
    • Meixner, A. and Sorin, D.J., Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures, 2006 International Conference on Dependable Systems and Networks (2006), pp. 10 pp. - [abs].
    • Bower, F.A. and Sorin, D.J. and Ozev, S., A mechanism for online diagnosis of hard faults in microprocessors, Proceedings. 38th Annual IEEE/ACM International Symposium on Microarchitecture (2006), pp. 12 pp. - [abs].
    • Meixner, A. and Sorin, D.J., Dynamic verification of sequential consistency, Proceedings. 32nd International Symposium on Computer Architecture (2005), pp. 482 - 93 [abs].
    • Dwyer, C. and Lebeck, A.R. and Sorin, D.J., Self-assembled architectures and the temporal aspects of computing, Computer (USA), vol 38 no. 1 (2005), pp. 56 - 64 [34] [abs].
    • Li, T. and Lebeck, A.R. and Sorin, D.J., Spin detection hardware for improved management of multithreaded systems, IEEE Trans. Parallel Distrib. Syst. (USA), vol 17 no. 6 (2006), pp. 508 - 21 [78] [abs].
    • Carter, J.R. and Ozev, S. and Sorin, D.J., Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown, Proceedings. Design, Automation and Test in Europe, vol Vol. 1 (2005), pp. 300 - 5 [abs].
    • Bower, F.A. and Shealy, P.G. and Ozev, S. and Sorin, D.J., Tolerating hard faults in microprocessor array structures, 2004 International Conference on Dependable Systems and Networks (2004), pp. 51 - 60 [abs].
    • Sorin, D.J. and Martin, M.M.K. and Hill, M.D. and Wood, D.A., SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, Proceedings 29th Annual International Symposium on Computer Architecture (2002), pp. 123 - 34 [ISCA.2002.1003568] [abs].