Daniel J. Sorin
W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
Dr. Daniel Sorin is the W.H. Gardner Jr. professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.
Appointments and Affiliations
- W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
- Professor of Electrical and Computer Engineering
- Professor in the Department of Computer Science
- Office Phone: (919) 660-5439
- Email Address: firstname.lastname@example.org
- Web Page:
- Ph.D. University of Wisconsin at Madison, 2002
- M.S. University of Wisconsin at Madison, 1998
- B.S. Duke University, 1996
The primary focus of my research is computer architecture. This research includes work to: improve the dependability of computer architectures, design microarchitectures such that their designs are easier to validate, and develop memory system designs for multicore processors.
Awards, Honors, and Distinctions:
- Best Paper Award. 20th International Symposium on High Performance Computer Architecture. 2014
- Lois and John L. Imhoff Distinguished Teaching Award. Pratt School of Engineering. 2011
- Eta Kappa Nu. Unknown. 2008
- Intel Graduate Fellowship. Unknown. 2008
- NSF Early CAREER Award. National Science Foundation. 2008
- Outstanding Graduate Research Award. University of Wisconsin. 2008
- Phi Beta Kappa. Unknown. 2008
- Tau Beta Pi. Unknown. 2008
- Top of 2004 - Nanocomputing Research. Technology Research News. 2008
- ECE 250L: Computer Architecture
- ECE 552: Advanced Computer Architecture I
- ECE 554: Fault-Tolerant and Testable Computer Systems
- ECE 652: Advanced Computer Architecture II
Representative Publications: (More Publications)
- Zhang, M; Bingham, JD; Erickson, J; Sorin, DJ, PVCoherence: Designing Flat Coherence Protocols for Scalable Verification, IEEE Micro, vol 35 no. 3 (2015), pp. 84-91 [10.1109/MM.2015.48] [abs].
- Jacobvitz, AN; Hilton, AD; Sorin, DJ, Multi-program benchmark definition, ISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software (2015), pp. 72-82 [10.1109/ISPASS.2015.7095786] [abs].
- Nathan, R; Sorin, DJ, Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores, IEEE Computer Architecture Letters, vol 14 no. 1 (2015), pp. 13-16 [10.1109/LCA.2014.2298391] [abs].
- Matthews, O; Zhang, M; Sorin, DJ, Scalably verifiable dynamic power management, Proceedings - International Symposium on High-Performance Computer Architecture (2014), pp. 579-590 [10.1109/HPCA.2014.6835967] [abs].
- Nathan, R; Anthonio, B; Lu, SL; Naeimi, H; Sorin, DJ; Sun, X, Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy, International Conference for High Performance Computing, Networking, Storage and Analysis, SC, vol 2015-January no. January (2014), pp. 117-127 [10.1109/SC.2014.15] [abs].