ECE Seminar: Introduction to VLSI Design and Education Center
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Friday, March 17, 2017 - 12:00pm to 1:00pm
Dr. Kunihiro Asada , Professor, Director, VLSI Design and Education Center, University of Tokyo, Japan
VLSI Design and Education Center (VDEC) was established in 1996 as an interuniversity center at the University of Tokyo. Its mission is somehow similar to MOSIS in US or Euro-practice in Europe; to support and promote LSI design activities in academia in terms of design environment, design training & LSI chip implementation. In the last 20 years statistics shows a rapid increase of the activities in Japan. About ten years ago VDEC extended its mission to cover micro/nanofabrication technologies (more-than-Moore) using a super cleanroom. VDEC is supporting fabrication facilities for lithography, etching and deposition, as well as open cleanroom space for research. These facilities are open for academia as well as industry. In this area VDEC is collaborating with oversea institutes.VDEC is also a research center of advanced LSI circuit design & design methodologies. There are three laboratories of LSI circuit, CAD & Test. These labs are studying issues of advanced LSI such as low voltage circuits, parameter variability, power integrity, formal design verification, parallel processing and post-production test. In this presentation current activities of VDEC will be introduced after reviewing a short summary of the history. As examples, two topics will be focused from the LSI circuit lab and Test lab; (1) an application of time-domain method for a clock and data recovery (CDR) circuit and (2) a supply voltage control method for ATE ATE to solve problems in post-production test.