ECE Seminar: Can we save Energy if we allow Errors in Computing?
Friday, September 1, 2017 - 12:00pm to 1:00pm
Janak H. Patel Professor Emeritus, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
A brief overview of present understanding of tradeoff between Energy and Errors in Computing will be presented. Prevailing understanding of a chip's behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore's Law. This understanding is challenged by a new hypothesis on the behavior of very large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to the new hypothesis. The new hypothesis states that in every large CMOS chip, there exist critical operations points (frequency, voltage) such that it divides the 2-D space (F, V) in to two distinct spaces: 1. Error-free operation and 2. Massive errors (i.e. completely inoperable). Two attempts at disproving this hypothesis with real physical experiments will be described. Some consequences of the hypothesis on energy savings in large data centers are also suggested.