Daniel J. Sorin

Research Themes

Trustworthy Computing

Research Interests

Computer architecture, designing microarchitectures so that they are easier to verify, improving computer system fault tolerance, developing memory systems for multicore processors, and designing special-purpose accelerators

Bio

Dr. Daniel Sorin is a professor of Electrical and Computer Engineering at Duke University. His research interests are primarily in computer architecture and dependability.

Education

• B.S. Duke University, 1996
• M.S. University of Wisconsin, Madison, 1998
• Ph.D. University of Wisconsin, Madison, 2002

Positions

• Professor of Electrical and Computer Engineering
• Bass Fellow
• Associate Chair of Education in the Department of Electrical and Computer Engineering
• Professor in Computer Science

Awards, Honors, and Distinctions

• Program Chair of HiPEAC 2017. HiPEAC. 2017
• Co-chair of selection committee for IEEE Micro's Top Picks 2016. IEEE Micro. 2016
• Associate Editor in Chief. Computer Architecture Letters. 2015
• IEEE Micro Top Pick. IEEE Micro. 2015
• Best Paper Award. 20th International Symposium on High Performance Computer Architecture. 2014
• IEEE Micro Top Pick. IEEE Micro. 2011
• Lois and John L. Imhoff Distinguished Teaching Award. Pratt School of Engineering. 2011
• ACM Senior Member. Association for Computing Machinery. 2009
• Intel Graduate Fellowship. Unknown. 2008
• NSF Early CAREER Award. National Science Foundation. 2008
• Top of 2004 - Nanocomputing Research. Technology Research News. 2008
• Outstanding Graduate Research Award. University of Wisconsin. 2008
• Phi Beta Kappa. Unknown. 2008
• Tau Beta Pi. Unknown. 2008
• Eta Kappa Nu. Unknown. 2008
• Faculty Early Career Development (CAREER) Program. National Science Foundation. 2005

Courses Taught

• ECE 554: Fault-Tolerant and Testable Computer Systems
• ECE 552: Advanced Computer Architecture I
• ECE 494: Projects in Electrical and Computer Engineering
• ECE 250D: Computer Architecture
• COMPSCI 393: Research Independent Study
• COMPSCI 391: Independent Study
• COMPSCI 250D: Computer Architecture

Publications

• Li W, Goens A, Oswald N, Nagarajan V, Sorin DJ. Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. In: Proceedings - International Symposium on Computer Architecture. 2024. p. 182–97.
• Mazurek F, Tschand A, Wang Y, Pajic M, Sorin D. Rigorous Evaluation of Computer Processors with Statistical Model Checking. In: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023. 2023. p. 1242–54.
• Oswald N, Nagarajan V, Sorin DJ, Gavrielatos V, Olausson TX, Carr R. HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro. 2023 Jul 1;43(4):62–70.
• Mehrabi A, Sorin DJ, Lee BC. Spatiotemporal Strategies for Long-Term FPGA Resource Management. In: Proceedings - 2022 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2022. 2022. p. 198–209.
• Oswald N, Nagarajan V, Sorin DJ, Gavrielatos V, Olausson T, Carr R. HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2022. p. 756–71.
• Sorin DJ. Reconfigurable Hardware in Postsilicon Microarchitecture. Computer. 2021 Mar 1;54(3):4–5.
• Mehrabi A, Lee D, Chatterjee N, Sorin DJ, Lee BC, O’Connor M. Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. In: Proceedings - 2021 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021. 2021. p. 48–58.
• Mehrabi A, Manocha A, Lee BC, Sorin DJ. Bayesian Optimization for Efficient Accelerator Synthesis. ACM Transactions on Architecture and Code Optimization. 2021 Jan 1;18(1).
• Murray S, Konidaris GD, Sorin DJ. Roadmap subsampling for changing environments. In: IEEE International Conference on Intelligent Robots and Systems. 2020. p. 5664–70.
• Archer S, Mappouras G, Calderbank R, Sorin D. Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. In: Proceedings - 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2020. 2020. p. 331–42.
• Oswald N, Nagarajan V, Sorin DJ. HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. In: Proceedings - International Symposium on Computer Architecture. 2020. p. 888–99.
• Sorin DJ. Computer Architecture for Orbital Edge Computing. Computer. 2020 Apr 1;53(4):7–8.
• Mehrabi A, Manocha A, Lee BC, Sorin DJ. Prospector: Synthesizing Efficient Accelerators via Statistical Learning. In: Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. 2020. p. 151–6.
• Nagarajan V, Sorin DJ, Hill MD, Wood DA. A Primer on Memory Consistency and Cache Coherence, Second Edition. Synthesis Lectures on Computer Architecture. 2020 Jan 1;15(1):1–294.
• Murray S, Floyd-Jones W, Konidaris G, Sorin DJ. A programmable architecture for robot motion planning acceleration. In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. 2019. p. 185–8.
• Mappouras G, Vahid A, Calderbank R, Sorin DJ. GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. In: Proceedings - 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2019. 2019. p. 1–12.
• Mappouras G, Vahid A, Calderbank R, Sorin DJ. Extending flash lifetime in embedded processors by expanding analog choice. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018 Nov 1;37(11):2462–73.
• Oswald N, Nagarajan V, Sorin DJ. ProtoGen: Automatically generating directory cache coherence protocols from atomic specifications. In: Proceedings - International Symposium on Computer Architecture. 2018. p. 247–60.
• Sorin DJ. Low-Power Content Addressable Memory. Computer. 2018 Mar 1;51(3):8–9.
• Mappouras G, Vahid A, Calderbank R, Hower DR, Sorin DJ. Jenga: Efficient fault tolerance for stacked DRAM. In: Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017. 2017. p. 361–8.
• Matthews O, Sorin DJ. Architecting hierarchical coherence protocols for push-button parametric verification. In: Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2017. p. 477–89.
• Matthews O, Bingham J, Sorin DJ. Verifiable hierarchical protocols with network invariants on parametric systems. In: Proceedings of the 16th Conference on Formal Methods in Computer-Aided Design, FMCAD 2016. 2017. p. 101–8.
• Sorin DJ. Persistent Memory. Computer. 2017 Mar 1;50(3):12.
• Murray S, Floyd-Jones W, Qi Y, Konidaris G, Sorin DJ. The microarchitecture of a real-Time robot motion planning accelerator. In: Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2016.
• Mappouras G, Vahid A, Calderbank R, Sorin DJ. Methuselah flash: Rewriting codes for extra long storage lifetime. In: Proceedings - 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2016. 2016. p. 180–91.
• Martin M, Sorin D. Top Picks from the 2015 Computer Architecture Conferences. IEEE Micro. 2016 May 1;36(3):6–9.
• Murray S, Floyd-Jones W, Qi Y, Sorin D, Konidaris G, Robotics D. Robot motion planning on a chip. In: Robotics: Science and Systems. 2016.
• Eslami A, Velasco A, Vahid A, Mappouras G, Calderbank R, Sorin DJ. Writing without disturb on phase change memories by integrating coding and layout design. In: ACM International Conference Proceeding Series. 2015. p. 71–7.
• Zhang M, Bingham JD, Erickson J, Sorin DJ. PVCoherence: Designing Flat Coherence Protocols for Scalable Verification. IEEE Micro. 2015 May 1;35(3):84–91.
• Jacobvitz AN, Hilton AD, Sorin DJ. Multi-program benchmark definition. In: ISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software. 2015. p. 72–82.
• Nathan R, Sorin DJ. Argus-G: Comprehensive, low-cost error detection for GPGPU cores. IEEE Computer Architecture Letters. 2015 Jan 1;14(1):13–6.
• Nathan R, Anthonio B, Lu SL, Naeimi H, Sorin DJ, Sun X. Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. In: International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 2014. p. 117–27.
• Matthews O, Zhang M, Sorin DJ. Scalably verifiable dynamic power management. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2014. p. 579–90.
• Zhang M, Bingham JD, Erickson J, Sorin DJ. PVCoherence: Designing flat coherence protocols for scalable verification. In: Proceedings - International Symposium on High-Performance Computer Architecture. IEEE Computer Society; 2014. p. 392–403.
• Nathan R, Sorin DJ. Nostradamus: Low-cost hardware-only error detection for processor cores. Proceedings -Design, Automation and Test in Europe, DATE. 2014;
• Nathan R, Sorin DJ. Nostradamus: Low-cost hardware-only error detection for processor cores. In: Proceedings -Design, Automation and Test in Europe, DATE. 2014.
• Sorin DJ, Matthews O, Zhang M. Architecting dynamic power management to be formally verifiable. Proceedings - Design Automation Conference. 2014 Jan 1;
• Badea C, Iures L, Sorin D. The recycling of fly ash to obtain building materials. In: International Multidisciplinary Scientific GeoConference Surveying Geology and Mining Ecology Management, SGEM. 2013. p. 473–8.
• Hechtman BA, Sorin DJ. Exploring memory consistency for massively-threaded throughput-oriented processors. Proceedings - International Symposium on Computer Architecture. 2013 Aug 12;201–12.
• Jacobvitz AN, Calderbank R, Sorin DJ. Coset coding to extend the lifetime of memory. Proceedings - International Symposium on High-Performance Computer Architecture. 2013 Jul 23;222–33.
• Seetharam K, Keh LCT, Nathan R, Sorin DJ. Applying reduced precision arithmetic to detect errors in floating point multiplication. Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC. 2013 Jan 1;232–5.
• Hechtman BA, Sorin DJ. Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software. 2013 Jan 1;118–9.
• Catalin B, Liana I, Ionel B, Sorin D. Building materials realised with fly ash. In: 12th International Multidisciplinary Scientific GeoConference and EXPO - Modern Management of Mine Producing, Geology and Environmental Protection, SGEM 2012. 2012. p. 661–5.
• Jacobvitz AN, Calderbank R, Sorin DJ. Writing cosets of a convolutional code to increase the Lifetime of Flash memory. 2012 50th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2012. 2012 Dec 1;308–18.
• Martin MMK, Hill MD, Sorin DJ. Why on-chip cache coherence is here to stay. Communications of the ACM. 2012 Jul 1;55(7):78–89.
• Lefebvre C, Lemouzy P, Sorin D, Roy G, Serbutoviez S. Building a roadmap for enhanced oil recovery prefeasibility study. In: Society of Petroleum Engineers - SPE Russian Oil and Gas Exploration and Production Technical Conference and Exhibition 2012. 2012. p. 160–90.
• Gizopoulos D, Psarakis M, Adve SV, Ramachandran P, Hari SKS, Sorin D, et al. Architectures for online error detection and recovery in multicore processors. Proceedings -Design, Automation and Test in Europe, DATE. 2011 May 31;533–8.
• Sorin DJ, Hill MD, Wood DA. A primer on memory consistency and cache coherence. Synthesis Lectures on Computer Architecture. 2011 Jan 1;16:1–212.
• Eibl PJ, Meixner A, Sorin DJ. An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. Performance Evaluation Review. 2011 Jan 1;39(1 SPEC. ISSUE):121–2.
• Romanescu B, Lebeck A, Sorin DJ. Address translation aware memory consistency. IEEE Micro. 2011 Jan 1;31(1):109–18.
• Zhang M, Lebeck AR, Sorin DJ. Fractal Coherence: Scalably verifiable cache coherence. In: Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2010. p. 471–82.
• Zhang M, Lebeck A, Sorin D. Fractal consistency: Architecting the memory system to facilitate verification. IEEE Computer Architecture Letters. 2010 Jul 1;9(2):61–4.
• Romanescu BF, Lebeck AR, Sorin DJ. Specifying and dynamically verifying address translation-aware memory consistency. In: International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2010. p. 323–34.
• Romanescu BF, Lebeck AR, Sorin DJ, Bracy A. Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2010.
• Romanescu BF, Lebeck AR, Sorin DJ. Specifying and dynamically verifying address translation-aware memory consistency. In: ACM SIGPLAN Notices. 2010. p. 323–34.
• Eibl PJ, Cook AD, Sorin DJ. Reduced precision checking for a floating point adder. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2009 Dec 1;145–52.
• Zhang M, Lungu A, Sorin DJ. Analyzing formal verification and testing efforts of different fault tolerance mechanisms. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2009 Dec 1;277–85.
• Lungu A, Bose P, Buyuktosunoglu A, Sorin DJ. Dynamic power gating with quality guarantees. Proceedings of the International Symposium on Low Power Electronics and Design. 2009 Nov 24;377–82.
• Lungu A, Bose P, Sorin DJ, German S, Janssen G. Multicore power management: Ensuring robustness via early-stage formal verification. 2009 7th IEEE-ACM International Conference on Formal Methods and Models for Co-Design, MEMOCODE ’09. 2009 Nov 19;78–87.
• Meixner A, Sorin DJ. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Transactions on Dependable and Secure Computing. 2009 Jan 1;6(1):18–31.
• Sorin DJ, Hill MD, Wood DA. Introduction to Consistency and Coherence. In: Synthesis Lectures on Computer Architecture. 2009. p. 1–7.
• Sorin DJ, Hill MD, Wood DA. Snooping Coherence Protocols. In: Synthesis Lectures on Computer Architecture. 2009. p. 99–138.
• Sorin DJ, Hill MD, Wood DA. Advanced Topics in Coherence. In: Synthesis Lectures on Computer Architecture. 2009. p. 177–95.
• Sorin DJ, Hill MD, Wood DA. Total Store Order and the x86 Memory Model. In: Synthesis Lectures on Computer Architecture. 2009. p. 37–50.
• Sorin DJ, Hill MD, Wood DA. Memory Consistency Motivation and Sequential Consistency. In: Synthesis Lectures on Computer Architecture. 2009. p. 17–36.
• Sorin DJ, Hill MD, Wood DA. Coherence Basics. In: Synthesis Lectures on Computer Architecture. 2009. p. 9–15.
• Sorin DJ, Hill MD, Wood DA. Directory Coherence Protocols. In: Synthesis Lectures on Computer Architecture. 2009. p. 139–76.
• Sorin DJ, Hill MD, Wood DA. Coherence Protocols. In: Synthesis Lectures on Computer Architecture. 2009. p. 83–97.
• Sorin DJ, Hill MD, Wood DA. Relaxed Memory Consistency. In: Synthesis Lectures on Computer Architecture. 2009. p. 51–81.
• Romanescu BF, Bauer ME, Ozev S, Sorin DJ. Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Conference on Computing Frontiers - Proceedings of the 2008 Conference on Computing Frontiers, CF’08. 2008 Dec 1;129–38.
• Romanescu BF, Sorin DJ. Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2008 Dec 1;43–51.
• Meixner A, Sorin DJ. Detouring: Translating software to circumvent hard faults in simple cores. Proceedings of the International Conference on Dependable Systems and Networks. 2008 Oct 13;80–9.
• Bower FA, Sorin DJ, Cox LP. The impact of dynamically heterogeneous multicore processors on thread scheduling. IEEE Micro. 2008 May 1;28(3):17–25.
• Meixner A, Bauer ME, Sorin DJ. Argus: Low-cost, comprehensive error detection in simple cores. IEEE Micro. 2008 Jan 1;28(1):52–9.
• Meixner A, Bauer ME, Sorin DJ. Argus: Low-cost, comprehensive error detection in simple cores. Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2007 Dec 1;210–22.
• Meixner A, Sorin DJ. Error detection using dynamic dataflow verification. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007 Dec 1;104–15.
• Lungu A, Sorin DJ. Verification-aware microprocessor design. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007 Dec 1;83–93.
• Ozev S, Sorin DJ, Yilmaz M. Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. 2007 IEEE International Conference on Computer Design, ICCD 2007. 2007 Dec 1;317–24.
• Romanescu BF, Bauer ME, Sorin DJ, Ozev S. Reducing the impact of process variability with prefetching and criticality-based resource allocation. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007 Dec 1;424.
• Yilmaz M, Meixner A, Ozev S, Sorin DJ. Lazy error detection for microprocessor functional units. In: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2007. p. 361–9.
• Meixner A, Sorin DJ. Unified microprocessor core storage. 2007 Computing Frontiers, Conference Proceedings. 2007 Oct 22;23–34.
• Meixner A, Sorin DJ. Error detection via online checking of cache coherence with token coherence signatures. Proceedings - International Symposium on High-Performance Computer Architecture. 2007 Aug 10;145–56.
• Bower FA, Sorin DJ, Ozev S. Online Diagnosis of Hard Faults in Microprocessors. ACM Transactions on Architecture and Code Optimization. 2007 Jan 1;4(2):8.
• Meixner A, Sorin DJ. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. Proceedings of the International Conference on Dependable Systems and Networks. 2006 Dec 22;2006:73–82.
• Sadler NN, Sorin DJ. Choosing an error protection scheme for a microprocessor's L1 data cache. IEEE International Conference on Computer Design, ICCD 2006. 2006 Dec 1;499–505.
• Bower FA, Hower D, Yilmaz M, Sorin DJ, Ozev S. Applying architectural vulnerability analysis to hard faults in the microprocessor. Performance Evaluation Review. 2006 Jun 1;34(1):375–6.
• Li T, Lebeck AR, Sorin DJ. Spin detection hardware for improved management of multithreaded systems. IEEE Transactions on Parallel and Distributed Systems. 2006 Jun 1;17(6):508–21.
• Yilmaz M, Hower DR, Ozev S, Sorin DJ. Self-checking and self-diagnosing 32-bit microprocessor multiplier. Proceedings - International Test Conference. 2006 Jan 1;
• Patwardhan JP, Dwyer C, Lebeck AR, Sorin DJ. NANA: A nano-scale active network architecture. ACM Journal on Emerging Technologies in Computing Systems. 2006 Jan 1;2(1):1–30.
• Carter JR, Ozev S, Sorin DJ. Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown. Proceedings -Design, Automation and Test in Europe, DATE ’05. 2005 Dec 1;I:300–5.
• Bower FA, Sorin DJ, Ozev S. A mechanism for online diagnosis of hard faults in microprocessors. Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2005 Dec 1;197–208.
• Meixner A, Sorin DJ. Dynamic verification of sequential consistency. Proceedings - International Symposium on Computer Architecture. 2005 Nov 10;482–93.
• Dwyer C, Lebeck AR, Sorin DJ. Self-assembled architectures and the temporal aspects of computing. Computer. 2005 Jan 1;38(1):56–64.
• Li T, Ellis CS, Lebeck AR, Sorin DJ. Pulse: A dynamic deadlock detection mechanism using speculative execution. In: USENIX 2005 Annual Technical Conference. 2005. p. 31–44.
• Bower FA, Ozev S, Sorin DJ. Autonomic microprocessor execution via self-repairing arrays. IEEE Transactions on Dependable and Secure Computing. 2005 Jan 1;2(4):297–310.
• Dwyer C, Cheung M, Sorin DJ. Semi-empirical SPICE models for carbon nanotube FET logic. 2004 4th IEEE Conference on Nanotechnology. 2004 Dec 1;386–8.
• Sorin DJ, Martin MMK, Hill MD, Wood DA. Using speculation to simplify multiprocessor design. Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM). 2004 Dec 1;18:1057–66.
• Dwyer C, Johri V, Cheung M, Patwardhan J, Lebeck A, Sorin D. Design tools for a DNA-guided self-assembling carbon nanotube technology. Nanotechnology. 2004 Sep 1;15(9):1240–5.
• Patwardhan JP, Lebeck AR, Sorin DJ. Communication breakdown: Analyzing CPU usage in commercial web workloads. In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software. 2004. p. 12–9.
• Bower FA, Shealy PG, Ozev S, Sorin DJ. Tolerating hard faults in microprocessor array structures. Proceedings of the International Conference on Dependable Systems and Networks. 2004 Jan 1;51–60.
• Sorin DJ, Hill MD, Wood DA. Dynamic Verification of End-to-End Multiprocessor Invariants. Proceedings of the International Conference on Dependable Systems and Networks. 2003 Dec 1;281–90.
• Li T, Lebeck AR, Sorin DJ. Quantifying instruction criticality for shared memory multiprocessors. In: Annual ACM Symposium on Parallel Algorithms and Architectures. 2003. p. 47–72.
• Sorin DJ, Lemon JL, Eager DL, Vernon MK. Analytic evaluation of shared-memory architectures. IEEE Transactions on Parallel and Distributed Systems. 2003 Feb 1;14(2):166–80.
• Li T, Lebeck AR, Sorin DJ. Quantifying instruction criticality for shared memory multiprocessors. In: Annual ACM Symposium on Parallel Algorithms and Architectures. 2003. p. 128–37.
• Alameldeen AR, Martin MMK, Mauer CJ, Moore KE, Xu M, Hill MD, et al. Simulating a $2M commercial server on a $2K PC. Computer (USA). 2003;36(2):50–7.
• Martin MMK, Harper PJ, Sorin DJ, Hill MD, Wood DA. Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 2003 Jan 1;206–17.
• Sorin DJ, Plakal M, Condon AE, Hill MD, Martin MMK, Wood DA. Specifying and verifying a broadcast and a multicast snooping cache coherence protocol. IEEE Transactions on Parallel and Distributed Systems. 2002 Jun 1;13(6):556–78.
• Martin MMK, Sorin DJ, Hill MD, Wood DA. Bandwidth adaptive snooping. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2002. p. 251–62.
• Sorin DJ, Martin MMK, Hill MD, Wood DA. SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 2002 Jan 1;123–34.
• Martin MMK, Sorin DJ, Cain HW, Hill MD, Lipasti MH. Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. Proceedings of the Annual International Symposium on Microarchitecture. 2001 Dec 1;328–37.
• Martin MMK, Sorin DJ, Ailamaki A, Alameldeen AR, Dickson RM, Mauer CJ, et al. Timestamp snooping: An approach for extending SMPs. International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2000 Dec 1;25–36.
• Martin MMK, Sorin DJ, Ailamaki A, Alameldeen AR, Dickson RM, Mauer CJ, et al. Timestamp snooping: An approach for extending SMPs. SIGPLAN Notices (ACM Special Interest Group on Programming Languages). 2000 Jan 1;35(11):25–36.
• Martin MMK, Sorin DJ, Ailamaki A, Alameldeen AR, Dickson RM, Mauer CJ, et al. Timestamp snooping: An approach for extending SMPs. Operating Systems Review (ACM). 2000 Jan 1;34(5):25–36.
• Eager DL, Sorin DJ, Vernon MK. AMVA techniques for high service time variability. Performance Evaluation Review. 2000 Jan 1;28(1):217–28.
• Bilir EE, Dickson RM, Hu Y, Plakal M, Sorin DJ, Hill MD, et al. Multicast snooping: A new coherence method using a multicast address network. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 1999 Jan 1;294–304.
• Condon AE, Hill MD, Plakal M, Sorin DJ. Using Lamport clocks to reason about relaxed memory models. IEEE High-Performance Computer Architecture Symposium Proceedings. 1999 Jan 1;270–8.
• Hill MD, Condon AE, Plakal M, Sorin DJ. System-level specification framework for I/O architectures. Annual ACM Symposium on Parallel Algorithms and Architectures. 1999 Jan 1;138–47.
• Sorin DJ, Pai VS, Adve SV, Vernon MK, Wood DA. Analytic evaluation of shared-memory systems with ILP processors. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 1998 Jan 1;380–91.
• Plakal M, Sorin DJ, Condon AE, Hill MD. Lamport clocks: verifying a directory cache-coherence protocol. Annual ACM Symposium on Parallel Algorithms and Architectures. 1998 Jan 1;67–76.

In The News

• A Crystal Ball for the Decade Ahead (Jan 9, 2020 | )